The invention relates to a semiconductor memory device and, more particularly, to processing on addresses and data mask information in the semiconductor memory device.
In conventional semiconductor memory devices, a pin is assigned separately for a data mask, and thus processing on addresses and data mask information has been carried out separately. FIG. 1 illustrates a block diagram of a part which receives and processes addresses in a conventional semiconductor memory device. The conventional semiconductor memory device includes a command buffer 101, a state machine 102, a write latency command unit 103, a clock buffer 104, an address buffer 105, an upward latch 106, an alignment unit 107, a downward latch 108, shift registers 109 and 110, and drivers 111 and 112.
In operation, commands are inputted to the command buffer 101 via a command (CMD) pin and addresses are applied to the address buffer 105 via an address pin. At this time, the addresses are inputted at both rising and falling edges of a clock. When a command is inputted to the state machine 102 through the command buffer 101, the state machine 102 recognizes that the inputted command is a command for write, and outputs a signal WCASP. In the meantime, an inputted address is latched by the upward latch 106 and the downward latch 108, respectively. An output of the upward latch 106 is aligned by the alignment unit 107 at the falling edge of the clock. In other words, addresses applied at the rising and falling edges of the clock are all aligned at the falling edge of the clock. The aligned addresses CA0 and CA1 are shifted by the shift registers 109 and 110. This is to synchronize the timing of a write latency (which is the time taken until receipt of data after a write command) with that of a write operation.
The signal WCASP is delayed by the write latency command unit 103 to generate an internal write signal IWT, which is a signal being enabled at the timing when a memory device writes data in a cell. And, addresses WCA0 and WCA1, which have been shifted and latched by the shift registers 109 and 110, are outputted, as addresses GAY0 and GAY1 indicative of global address Y, through the drivers 111 and 112 in synchronism with the internal write signal IWT.
FIG. 2 is a timing diagram illustrating the operation of the semiconductor memory device described in FIG. 1. When addresses A0 and A1 are inputted together with a write command WT, data Q0 to Q7 are applied after the write latency. The inputted addresses are aligned into addresses CA0 and CA1 by the latches 106 and 108 and the alignment unit 107 and then shifted to addresses WCA0 and WCA1 by the shift registers 109 and 110. Further, an internal write signal IWT is enabled at the timing when the memory device writes data in a memory cell, and addresses are outputted as the global addresses GAY0 and GAY1 through the drivers 111 and 112 in synchronism with the internal write signal IWT.
As indicated above, the conventional semiconductor memory device processes address information by using the configuration shown in FIG. 1, but processes data mask information in a different manner. Because the addresses and the data mask information are processed separately, a relatively large-sized circuit is required.